In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.

Contributions are welcome to add new problems, improve solutions, and help fix issues.

RISC-V Instruction Set Manual

A collection of Master XDC files for Digilent FPGA and Zynq boards.

PicoRV32 - A Size-Optimized RISC-V CPU

An FPGA-accelerated High-Frequency Trading design on the Xilinx Zynq-7020 (PYNQ-Z2)

XLS: Accelerated HW Synthesis

Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)

Issues and discussions around RISC-V support in AOSP.

Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms

NVDLA Web Content

Verification of Advanced Encryption Standard (AES-128) Using the Universal Verification Methodology (UVM).

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

RTL, Cmodel, and testbench for NVDLA

Convolutional accelerator kernel, target ASIC & FPGA

Multi-platform nightly builds of open source digital design and verification tools

SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows

RISC-V CPU Core (RV32IM)

I made an AES-128 bit Encryption Core on my FPGA for my Hardware Security 1 class using the Nexys A7 board

Free Courses,links,Notes,Cheatsheets,previous year solved questions and lot more...

Open-source Verilog RTL NPU for AI acceleration, research, and silicon experimentation

Interview Experience

Collection of Summer 2026 tech internships!

Everything required to run your own Base node

provides metadata for networkIDs and chainIDs

A tool for token-curated communities.

Verify Cairo contracts on Starkscan in 1 minute.