VHDL 2008/93/87 simulator

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

VUnit is a unit testing framework for VHDL/SystemVerilog

The PoC Library has been forked to github.com/VHDL/PoC. See new address below

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

SNES for the Analogue Pocket

VHDL synthesis (based on ghdl)

Opensource software/hardware platform to build edge AI solutions deployed on FPGA or custom ASIC hardware.

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

ZPUino HDL implementation

A Pac-Man Arcade implementation for the TangNano9K using HDMI

An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.

VHDL PCIe Transceiver

F18A source HDL

Design and implementation of a complete ARM based CPU.

The DECA Development Kit presents a robust hardware design platform built around the Altera MAX 10 FPGA.

Reference Projects for TE0720 ZYNQ module

Fork of a RISC-V compliant CPU, which originated in a project at the HAW Hamburg

A 16 bit softcore processor implemented in VHDL

PCIe AXI DMA

A simple ALU, FSM and registers implemented in VHDL.