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OpenTitan: Open source silicon root of trust

SystemVerilog 3,016 910 Updated Nov 10, 2025

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

SystemVerilog 1,136 480 Updated May 26, 2025

A directory of Western Digital’s RISC-V SweRV Cores

SystemVerilog 872 134 Updated Mar 26, 2020

A Linux-capable RISC-V multicore for and by the world

SystemVerilog 744 194 Updated Nov 8, 2025