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1. AXI4-RISCV-UVM AXI4-RISCV-UVM Public

   RISC-V SoC verification project using SystemVerilog, AXI4-style DMA, SVA, UVM monitors, scoreboards, and functional coverage.

   SystemVerilog 1

2. pipelined-cordic-accelerator pipelined-cordic-accelerator Public

   16-stage SystemVerilog CORDIC sine/cosine accelerator with Q2.14 fixed-point arithmetic, valid-ready backpressure, Python golden-model verification, assertions, benchmarking and Vivado Artix-7 tim…

   SystemVerilog

3. Credit-Based-NoC-Router-Arbiter-with-SVA-Formal-Verification Credit-Based-NoC-Router-Arbiter-with-SVA-Formal-Verification Public

   Credit-based NoC output-port arbiter with SystemVerilog RTL, SVA formal proofs, bounded fairness checks, cover properties, and counterexample debug using SymbiYosys/Yosys/SMTBMC.

   SystemVerilog

4. memory-subsystem-rtl-verification memory-subsystem-rtl-verification Public

   Designed a high-performance cache memory subsystem with ECC (SEC-DED) and built-in self-test (BIST) for reliability and fault coverage. Developed a SystemVerilog verification environment with error…

   SystemVerilog

5. Neurosense Neurosense Public

   Wearable health monitor and sleep stage detector

   Jupyter Notebook

6. p3dx-top p3dx-top Public

   Forked from datakaveri/p3dx-top

   TOP - TEE Orchestrator Protocol

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