RISC-V CPU Core (RV32IM)

RISC-V XV6/Linux SoC, marchID: 0x2b, 0x34

A tiny Open POWER ISA softcore written in VHDL 2008

Opensource DDR3 Controller

FuseSoC-based SoC for VeeR EH1 and EL2

Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps

This code is used to connect the OV7670 Camera to a NEXYS4 and then display the image on a monitor in Verilog

Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board

The 64 bit OpenPOWER Microwatt core, MPW1 tape out

A blinky project for the ULX3S v3.0.3 FPGA board