This project implements a simple nanoprocessor using VHDL. The design is modular, with each component responsible for a specific function in the processor's operation. The project is suitable for FPGA implementation and educational purposes.

• Nano_processor.vhd: Top-level entity integrating all modules of the nanoprocessor.
• Top_Module.vhd: Main wrapper for the nanoprocessor, handling I/O and system integration.
• Instruction_Decoder.vhd: Decodes instructions from memory for processor control.
• Instruction_memory.vhd: Stores and outputs instructions based on address input.
• Register_Memory.vhd: Implements the register file for data storage and access.
• Add_Sub_4bit_unit.vhd: 4-bit adder/subtractor unit for arithmetic operations.
• Adder_3bit.vhd: 3-bit adder, used in the counter module.
• FA.vhd: Full Adder module, used in arithmetic units.
• HA.vhd: Half Adder module, used in arithmetic units.
• Counter.vhd: 3-bit counter for memory addressing and sequencing.
• Decoder_2_to_4.vhd: 2-to-4 line decoder for address decoding.
• Decoder_3_to_8.vhd: 3-to-8 line decoder for address decoding.
• MUX_2way_3bit.vhd: 2-to-1 multiplexer for 3-bit data.
• MUX_2way_4bit.vhd: 2-to-1 multiplexer for 4-bit data.
• MUX_8way_4bit.vhd: 8-to-1 multiplexer for 4-bit data.
• Register_4_bit.vhd: 4-bit register for temporary data storage.
• LUT_7Seg.vhd: Look-up table for 7-segment display output.
• Slow_clock.vhd: Clock divider to generate a slower system clock.

Testbenches for each module are provided in the sim/ directory. These files can be used to verify the functionality of each component individually.

To use or simulate the nanoprocessor, instantiate the Top_Module or Nano_processor entity in your FPGA project, and connect the appropriate I/O signals. Use the provided testbenches for simulation and verification.