Starred repositories
A quick tutorial on generating planet-like meshes in Godot
Version 3 of my educational DIY TTL computer built around a UART serial interface - now with blinkenlights!
Kielan / Salt-C4M_FlexLibs
Forked from FatsieFS/Salt-C4M_FlexLibsKLayout salt package for PDKMaster based Chips4Maker's flexible and scalable libraries.
Kielan / CH32V203-USBCDC
Forked from 21km43/CH32V203-USBCDCUSB-CDC (Universal Serial Bus Composite Devic Class) for CH32V203
Kielan / JonG-s-Rust-Lox-Interpereter
Forked from jonhoo/loxhttps://app.codecrafters.io/courses/interpreter
An open-source static random access memory (SRAM) compiler.
Kielan / caravel
Forked from efabless/caravelCaravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
https://caravel-user-project.readthedocs.io
https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open processes.
SRAM macros created for the GF180MCU provided by GlobalFoundries.
XCircuit circuit drawing and schematic capture tool
PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already installed and ready to use.
iic-jku / IIC-OSIC-TOOLS
Forked from efabless/foss-asic-toolsIIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.
sifferman / spice-to-sch
Forked from eliahreeves/spice2schA CLI to convert SkyWater SKY130 spice files into xschem .sch files.
Verified visual schematics for all SKY130 Cells
Verified visual schematics for all SKY130 Cells
XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.
A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.