A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

Design and implementation of an 8-bit SAR (Successive Approximation Register) ADC

Simple implementation of cache using VHDL

BYU Pynq PR Video Pipeline Hardware

The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

Lime Digital Function Blocks

Public repository for all designs used in the Systems-on-Chip Programming Project at EPFL (CS-309)

SPI Master RTL on fpga. ESP32 was the slave. highly reliable, tested upto 10MHz and 512 bits for transaction length

JPEG Compression algorithm implemented in FPGA with VHDL. SPI Master was also implemented in VHDL to extract result

Single and multi cycle MIPs CPUs in VHDL

Processor supporting ARM architecture made in VHDL as a part of COL216 - Computer Architecture

Random FPGA Projects

First exposure to VHDL and FPGAs!

Reads and parses data from IWR6843AOP and streams it

Contains Projects Written for the Spartan III (X3S50A) FPGA in VHDL

VHDL-2008 Support Library

VHDL synthesis (based on ghdl)

This repository contains HDL designs I have created / ported over the years

A pipelined MIPS-Lite CPU implementation

Mealy Machine with VHDL