Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

NUDT硕士博士毕业论文latex模板

A template project for beginning new Chisel work

The OpenPiton Platform

The root repo for lowRISC project and FPGA demos.

Minimised environment for bandwidth limited sites

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Berkeley's Systolic Array Generator

Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator

A collection of Master XDC files for Digilent FPGA and Zynq boards.

A simple 5-stage Pipeline RISC-V core

Minkowski Engine is an auto-diff library for generalized sparse convolutions and high-dimensional sparse tensors

Open Source Software for Developing on the Freedom E Platform

If you want to keep a secret, you must also hide it from yourself.

BOOM: Berkeley Out-of-Order Machine

Rocket Chip Generator

educational microarchitectures for risc-v isa

Ariane is a 6-stage RISC-V CPU capable of booting Linux

Simple RISC-V 3-stage Pipeline in Chisel

Source files for SiFive's Freedom platforms

RISC-V Tools (ISA Simulator and Tests)

Support for Rocket Chip on Zynq FPGAs

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel