Basic-Verilog

Few Verilog Programs I had wrote for EC-220 Computer System Architecture

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
2X1MUX.v		2X1MUX.v
32Bit Register.v		32Bit Register.v
ALU.v		ALU.v
CU.v		CU.v
Control Unit FSM.v		Control Unit FSM.v
Counter.v		Counter.v
DFlipFlop Using NOR.v		DFlipFlop Using NOR.v
DFlipFlop.v		DFlipFlop.v
Decoding Unit.v		Decoding Unit.v
IrtazaModule.v		IrtazaModule.v
Lab5.v		Lab5.v
MCP.v		MCP.v
Memory.v		Memory.v
PIPO.v		PIPO.v
PISO.v		PISO.v
README.md		README.md
RegFile.v		RegFile.v
RegisterFile.v		RegisterFile.v
RightShiftRegister.v		RightShiftRegister.v
SIPO.v		SIPO.v
SISO.v		SISO.v
Single Cycle Processor.v		Single Cycle Processor.v
TFlipFlop.v		TFlipFlop.v
Task1.v		Task1.v
Task2		Task2
Task7.v		Task7.v
test.v		test.v

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