The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

RISC-V Speculation Barrier

The ultimate VCD files comparator

Revizor - Hardware fuzzing for the age of speculation

Docker sources for the artifacts of MileSan

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations

🦀 No-nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl

Fast Symbolic Repair of Hardware Design Code

Instruction Set Generator initially contributed by Futurewei

HybriDIFT: Scalable Memory-Aware Dynamic Information Flow Tracking for Hardware