SCR1 is a high-quality open-source RISC-V MCU core in Verilog

VeeR EH1 core

A directory of Western Digital’s RISC-V SweRV Cores

training labs and examples

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Examples and reference for System Verilog Assertions

Virtio implementation in SystemVerilog