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Lex for SystemVerilog

C 1 Updated May 3, 2026
C 1 Updated Dec 24, 2024

Proof of concept of embedding a DSL into SystemVerilog

SystemVerilog 2 Updated May 9, 2026

BNF Converter

TeX 1 Updated May 9, 2026

Embed JSON in SystemVerilog

SystemVerilog 1 Updated May 9, 2026

This is a SystemVerilog configuration class generation -- from JSON schema -- utility.

Python 1 Updated May 10, 2026

Functional Reactive DSL in Haskell that compiles to JavaScript.

Haskell 20 Updated Jun 14, 2009