INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.

Codebase for reproducible benchmarking experiments in MedMNIST v2

Unified Efficient Fine-Tuning of 100+ LLMs & VLMs (ACL 2024)

Fast and memory-efficient exact attention

Verilog evaluation benchmark for large language model

This is a python repo for flattening Verilog

This project is an upgraded version of FlattenRTL, designed to more efficiently flatten Verilog designs and generate a more readable Verilog file by leveraging Verilator. (ISEDA 24)

Utils for Unsloth https://github.com/unslothai/unsloth

Fine-tuning & Reinforcement Learning for LLMs. 🦥 Train OpenAI gpt-oss, DeepSeek-R1, Qwen3, Gemma 3, TTS 2x faster with 70% less VRAM.

Many studies have shown that the performance on deep learning is significantly affected by volume of training data. The MedicalNet project provides a series of 3D-ResNet pre-trained models and rela…

A Code Playground That Just Works!

An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs

A spacedesk client app that can be used offline.

Homework Submission, Automated Grading, and TA grading system.

Verilog auto debug with Gpts

Craft AI-driven interfaces effortlessly 🤖

🍼 Plugin driven WYSIWYG markdown editor framework.