🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

A work-in-progress for what is to be a software-free web server for static content.

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.

A huge VHDL library for FPGA and digital ASIC development

🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

Flexible VHDL library

Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL

Basic RISC-V CPU implementation in VHDL.

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

Portable HyperRAM controller

A translation of the Xilinx XPM library to VHDL for simulation purposes

IEEE 754 single precision floating point library in systemverilog and vhdl

An all-digital GPS disciplined oscillator using MMCM phase shift.

DMA source and sink blocks for Xilinx Zynq FPGAs

Connecting FPGA and MCU using Ethernet RMII

Lightweight RiscV core, VHDL only

YM2151 : Step-by-step implementation

Configurable RISC-V core