xezim is a SystemVerilog simulator written in Rust designed for experimentation, learning, and exploring AI-assisted chip design workflows.

xezim was previously developed under the name sisSIM. The binary, library, and compiled-artifact magic were renamed in place; behavior is unchanged.

This project explores whether modern tools and AI can dramatically reduce the complexity of building core EDA infrastructure such as simulators.

The simulator parses SystemVerilog source code, builds an internal representation, and executes simulations for combinational and sequential logic.

Traditional EDA tools require very large engineering teams and many years of development.

This project explores a key question:

Can a small team — or even a single engineer with AI assistance — build core EDA tools such as a SystemVerilog simulator?

The simulator is being developed incrementally, starting from simple combinational logic and gradually adding more SystemVerilog features.

Current capabilities include:

• IEEE 1800-2023 grammar by default (--sv2017 opts back to the earlier edition)
• SystemVerilog module parsing
• Signal and net representation
• Continuous assignments
• Basic expression evaluation
• Combinational logic simulation
• Sequential simulation infrastructure
• Test execution framework
• Waveform / trace dumps — VCD ($dumpfile/$dumpvars), XTrace v1.0 (--xtrace, optional zstd compression + scope filtering), and AITRACE-T (--aitrace)
• UVM 1.2 runtime support with -DUVM_NO_DPI, demonstrated by running the riscv-dv instruction generator end-to-end (random RV32IMC programs that assemble cleanly with riscv64-unknown-elf-as -march=rv32imc_zicsr_zifencei)
• Event-driven edge gating (XEZIM_EVENT_EDGE=1) — opt-in skip of clocked flop fires whose data inputs haven't changed; 1.13-1.30× wall on the C910 / C906 hello / memcpy / cmark benchmarks, correct-by-construction

xezim is split across two repos; xezim-core is vendored here as a submodule:

xezim-core/   — shared library: parser, elaboration, value, SDF, VCD sink (submodule)
./            — bytecode interpreter + simulator (this repo, binary: xezim)

This repo:

.
├── src/
│   ├── compiler/
│   │   ├── simulator.rs   — event-driven simulator + bytecode VM
│   │   ├── bytecode.rs    — bytecode compiler for cont_assigns and always blocks
│   │   └── mod.rs         — re-exports value/elaborate/sdf from xezim-core
│   ├── lib.rs             — wraps xezim_core::parse_and_elaborate_multi + Simulator
│   └── main.rs            — CLI entry point (binary: xezim)
├── tests/                 — Rust integration tests + SV compliance suite
├── examples/
└── Cargo.toml             — depends on xezim-core (path = xezim-core, a submodule)

Parser & elaboration — live in xezim-core; consumed by both xezim and xezim-b.

Simulator — event-driven VM over a bytecode lowering of cont_assigns and always blocks.

Native compiler (xezim-b) — AOT-lowers an elaborated design to Rust and links a standalone binary.

End-to-end TEST PASSED with bit-identical results vs the workloads' own golden expectations:

Many test cases are included to validate functionality.

Credit: All pr*.v tests were taken from the Icarus Verilog test suite.

These tests help verify correctness against real-world Verilog/SystemVerilog edge cases.

Install Rust: https://www.rust-lang.org/tools/install

xezim-core is vendored as a git submodule under this repo (xezim-core/, referenced by path = "xezim-core"), so clone recursively:

git clone --recursive git@github.com:<you>/xezim.git
cd xezim
# (if already cloned non-recursively: git submodule update --init)

Build the simulator:

cargo build            # debug
cargo build --release  # optimized (recommended for large designs)

The release binary is produced at target/release/xezim.

Run a simple example via cargo:

cargo run --release -- examples/test.sv

Or invoke the binary directly:

./target/release/xezim <source_files> [+plusargs] [options]

Common options:

Selected env knobs (off by default unless noted):

Example — run the picorv32 testbench against a gate-level netlist:

./target/release/xezim testbench.v synth.v \
    +firmware=firmware/firmware.hex --max-time 50000000

Typical development loop:

edit code
↓
cargo build
↓
run tests
↓
add new SystemVerilog features

Rust provides strong guarantees for memory safety and concurrency, making it well suited for building large-scale EDA infrastructure.

This project explores several long-term ideas:

• AI-assisted EDA development
• Rapid simulator prototyping
• Cloud-scale simulation
• Distributed multi-CPU simulation

The goal is to investigate whether modern software and AI tools can dramatically accelerate the creation of chip design infrastructure.

Apache License 2.0

See the LICENSE file for details.

• Icarus Verilog project for the public test suite
• The Rust community
• Open-source EDA projects