[WIP] Open-source DFT flow

V-Mate is a RISC V core processor developed by Hu-mind.AI VLSI Teammates tool.

SystemVerilog (IEEE 1800-2017) Simulator

Modular hardware build system

A fuzzer for ML compilers

The Zylin ZPU

HARC: verification language compiler, sister to ARCH

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Condor Computing's fork of Spike with STF and BBV support, Spike-STF

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

ASIC implementation flow infrastructure, successor to OpenLane

Digital HDL Design Full-stack Agents

Alliance VLSI CAD Tools (LIP6)

open source hardware synthesis. SystemVerilog, VHDL and ABEL-HDL to gate-level netlists

Run agents like Hermes and OpenClaw more securely inside NVIDIA OpenShell with managed inference

A lightweight alternative to OpenClaw that runs in containers for security. Connects to WhatsApp, Telegram, Slack, Discord, Gmail and other messaging apps,, has memory, scheduled jobs, and runs dir…

SystemVerilog file list pruner

Natural Language Exploration of Hardware Designs and Libraries (ICLAD'25) -- Best Paper Award

The SBOM tool is a highly scalable and enterprise ready tool to create SPDX 2.2 compatible SBOMs for any variety of artifacts.

A fast VHDL language server and analysis library written in Rust

The open source coding agent.

MCP Server for Ghidra

Claude Opus 4.6 wrote a dependency-free C compiler in Rust, with backends targeting x86 (64- and 32-bit), ARM, and RISC-V, capable of compiling a booting Linux kernel.

Use graph neural network to predict power, timing and area of a digital system.

LEC - Logic Equivalence Checking - Formal Verification

LLM-Assisted Hardware Formal Verification Tool

HDL libraries and projects

A Verilog synthesis flow for Minecraft redstone circuits