Stars
Claude Opus 4.6 wrote a dependency-free C compiler in Rust, with backends targeting x86 (64- and 32-bit), ARM, and RISC-V, capable of compiling a booting Linux kernel.
Use graph neural network to predict power, timing and area of a digital system.
LEC - Logic Equivalence Checking - Formal Verification
A Verilog synthesis flow for Minecraft redstone circuits
A machine learning accelerator core designed for energy-efficient AI at the edge.
CRCat: Complex Rational Catalog of all Possible RLC Networks of up to and Including Five Elements
Manage headless displays with Xvfb (X virtual framebuffer)
TuRTLe: A Unified Evaluation of LLMs for RTL Generation 🐢 (MLCAD 2025)
A SystemVerilog language server based on the Slang library.
TensorZero is an open-source stack for industrial-grade LLM applications. It unifies an LLM gateway, observability, optimization, evaluation, and experimentation.
akashlevy / OpenRRAM
Forked from VLSIDA/OpenRAMAn open-source resistive random access memory (RRAM) compiler based on OpenRAM.
Evaluating accuracy on quantized DNNs using RRAM as weight storage
A 28-page detailed study guide for the Princeton course "Networks: Friends, Money, and Bytes" (ELE 381/COS 381). Also useful for "Networked Life: 20 Questions and Answers" textbook by Mung Chiang
Measurements and simulations of nMOS test device for EE312 at Stanford University
A 28-page detailed study guide for the Princeton course "Computer Architecture" (ELE 475/COS 475). Covers most topics in H&P5 as well.
A minimal tensor processing unit (TPU), inspired by Google's TPU V2 and V1
Python wrapper to interact with TCL command line interfaces
Kythe is a pluggable, (mostly) language-agnostic ecosystem for building tools that work with code.
ADC Performance Survey (ISSCC & VLSI Circuit Symposium)
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
An open source CPU design and verification platform for academia
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.