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Yosys SystemVerilog Parser - UHDM 2 RTLIL Yosys Pass
Claude Code is an agentic coding tool that lives in your terminal, understands your codebase, and helps you code faster by executing routine tasks, explaining complex code, and handling git workflo…
This is the development repository for the OpenFHE library. The current version is 1.5.1 (released on April 10, 2026).
Compiler backend from packing to bitstream generation.
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
ABC: System for Sequential Logic Synthesis and Formal Verification
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Modular hardware build system
ANTLR (ANother Tool for Language Recognition) is a powerful parser generator for reading, processing, executing, or translating structured text or binary files.
Plugins for Yosys developed as part of the F4PGA project.
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
Test suite designed to check compliance with the SystemVerilog standard.
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
alainmarcel / Surelog
Forked from chipsalliance/SurelogSystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
A beautiful stack trace pretty printer for C++
Cap'n Proto serialization/RPC system - core tools and C++ library
FlatBuffers: Memory Efficient Serialization Library
Ideas that need engineering-power from the community for UHDM/Surelog/Related topics