Open Logic FPGA Standard Library

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

A JSON library implemented in VHDL.

A translation of the Xilinx XPM library to VHDL for simulation purposes

A simple AXI4 SPI master with optional GPIO for additional control.

Emacs VHDL Tree-sitter Major-mode

IP core for a simple SPI master with variable clock frequncy within AXI peripheral. Developed and tested on Zybo evaluation board (Zynq-7000 product family)

Bitonic Sorter Network written in VHDL