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1. I2C_Protocol I2C_Protocol Public

   I2C Protocol implementation using Verilog

   Verilog 4

2. Floating-Point-Adder-and-Multiplier Floating-Point-Adder-and-Multiplier Public

   Implementation of Single-Precision(32-bit) Floating Point adder and Multiplier

   Verilog 2

3. RISC-V-Single-Cycle-Core RISC-V-Single-Cycle-Core Public

   Processes a single 32-bit instruction in a single clock cycle. Based on the RISV-32 ISA supporting addition, subtraction, bitwise AND & OR operations. Based on the Harvard Architecture and Single-C…

   Verilog 1

4. AXI-Lite-DMA-Controller AXI-Lite-DMA-Controller Public

   AXI Lite Protocol implemented through a DMA master, Slave and a synchronous FIFO

   Verilog 1

5. RISC-V_Pipelined-Core RISC-V_Pipelined-Core Public

   RISC-V 32-bit ISA supported 5-staged Pipelined Core including a Hazard Control Unit implemented using Verilog. Based on the Harvard Architecture and Pipelined Microarchitecture

   Verilog 1 1

6. BCD-Up-Down-Counter BCD-Up-Down-Counter Public

   BCD Up/Down Counter Using Verilog

   SystemVerilog