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564 followers · 31 following

Achievements

Achievement: Galaxy BrainAchievement: Starstruckx4Achievement: Pair Extraordinairex2Achievement: QuickdrawAchievement: YOLOAchievement: Pull Sharkx4Achievement: Arctic Code Vault Contributor

Achievements

Achievement: Galaxy BrainAchievement: Starstruckx4Achievement: Pair Extraordinairex2Achievement: QuickdrawAchievement: YOLOAchievement: Pull Sharkx4Achievement: Arctic Code Vault Contributor

Organizations

@ucb-bar @riscv @sifive @freechipsproject @chipsalliance

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Stars

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aswaterman / trainwreck

Original RISC-V 1.0 implementation. Not supported.

Verilog 42 15 Updated Oct 4, 2018

andrewmd5 / Borderless-Gaming

Play your favorite games in a borderless window; no more time consuming alt-tabs.

C# 6,391 592 Updated Sep 5, 2025

rui314 / mold

mold: A Modern Linker 🦠

C++ 16,364 533 Updated Apr 7, 2026

riscv-software-src / riscv-isa-sim

Spike, a RISC-V ISA Simulator

C 3,064 1,050 Updated Apr 12, 2026

riscv / riscv-isa-manual

RISC-V Instruction Set Manual

TeX 4,569 816 Updated Apr 13, 2026

chipsalliance / chisel

Chisel: A Modern Hardware Design Language

Scala 4,631 651 Updated Apr 11, 2026

chipsalliance / firrtl

Flexible Intermediate Representation for RTL

Scala 749 180 Updated Aug 20, 2024

sifive / freedom

Source files for SiFive's Freedom platforms

Scala 1,148 282 Updated Dec 22, 2025

chipsalliance / rocket-chip

Rocket Chip Generator

Scala 3,737 1,249 Updated Feb 25, 2026