Rust crate that publishes XLSynth capabilities (wrapping libxlsynth.so/.dylib)

SystemVerilog compiler and language services

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Stitch together Verilog modules with Rust

XLS DSLX Language Support for Visual Studio Code

XLS DSLX Language Support for Visual Studio Code

Export Github repository issues, pull requests and comments to markdown.

ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

XLS: Accelerated HW Synthesis

Starlark implementation of bazel rules for CUDA.

A framework that support executing unmodified CUDA source code on non-NVIDIA devices.

Stores documents and resources used by the OpenXLA developer community

fakeram generator for use by researchers who do not have access to commercial ram generators

Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)

SonicBOOM: The Berkeley Out-of-Order Machine

git-pr-chain

Python meta-circular evaluator.

A remote cache for Bazel

Stabilizer: Rigorous Performance Evaluation

Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.

妖刀夢渡

A static type analyzer for Python code

Abseil Common Libraries (C++)

A self-contained JavaScript wiki for the browser, Node.js, AWS Lambda etc.

Composable transformations of Python+NumPy programs: differentiate, vectorize, JIT to GPU/TPU, and more

This is a simple UART echo test for the iCEstick Evaluation Kit