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Apple Firestorm/Icestorm CPU microarchitecture docs
A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
educational microarchitectures for risc-v isa
🌵 A responsive, clean and simple theme for Hexo.
A cache simulator, using the C++ language, to simulate a direct-mapped, fully associative and set-associative cache. It has a set of memory reference generators to generate different sequences of r…
A simple command-line Sudoku solver in C for educational purposes
Learn how to design large-scale systems. Prep for the system design interview. Includes Anki flashcards.
Hardware-accelerated Multi-threaded IOTA PoW, drop-in replacement for ccurl
Working draft of the proposed RISC-V V vector extension
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
"Mind the cache" presentation at using std::cpp 2015 and associated material
Master programming by recreating your favorite technologies from scratch.
POW node to do GPU POW for IOTA using ccurl
Instagram in terminal 👽👽🔥🔥
计算机速成课（播放量 496.2 万） （共40集，每一集 10 分钟）2018 年完成翻译。评论区有大量好评