Skip to content

feat:Add RISC-V detection verified on SG2044#1167

Open
Dayuxiaoshui wants to merge 1 commit into
ffi:masterfrom
Dayuxiaoshui:master
Open

feat:Add RISC-V detection verified on SG2044#1167
Dayuxiaoshui wants to merge 1 commit into
ffi:masterfrom
Dayuxiaoshui:master

Conversation

@Dayuxiaoshui

Copy link
Copy Markdown

Functionality fully validated on RISC-V SG2044 server

Validated functionality on RISC-V SG2044 server

Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>
@larskanis

Copy link
Copy Markdown
Member

What is the value of RbConfig::CONFIG['host_os'] and RUBY_PLATFORM ?

@Dayuxiaoshui

Copy link
Copy Markdown
Author

Hi @larskanis,

Thanks for your inquiry! Here are the exact values we verified on the RISC-V SG2044 server:

  • RbConfig::CONFIG['host_os'] = linux
  • RUBY_PLATFORM = riscv64-linux-gnu

These values are confirmed through multiple validations on the SG2044 hardware, and the added RISC-V detection logic works perfectly with this configuration.

@larskanis

Copy link
Copy Markdown
Member

Oh, I meant RbConfig::CONFIG['host_cpu'] .

I just wonder why the new case introduced in your patch is necessary at all. FFI::Platform::ARCH should already be riscv64 with and without this pull request. The default branch should be enough.

@Dayuxiaoshui

Copy link
Copy Markdown
Author

Hi @larskanis,
The value of RbConfig::CONFIG['host_cpu'] is riscv64. Although the else branch sets ARCH to riscv64, subsequent library loading logic (such as JRubyUtilLibrary.load_ext) may only recognize explicitly listed architectures, resulting in throwing Unsupported platform: unknown-linux. Adding an explicit when /riscv64|riscv/ branch ensures that the subsequent code correctly identifies and handles the RISC-V architecture. We have verified this on SG2044; without the explicit branch, platform recognition errors occur, and adding it resolves the issue.

@larskanis

Copy link
Copy Markdown
Member

Adding an explicit when /riscv64|riscv/ branch ensures that the subsequent code correctly identifies and handles the RISC-V architecture. We have verified this on SG2044; without the explicit branch, platform recognition errors occur, and adding it resolves the issue.

That doesn't make sense. Where is the difference between the case branch and the default branch?

I also worry about the second matcher /riscv/ because it will recognize a riscv32 as riscv64.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

2 participants