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Verilator open-source SystemVerilog simulator and lint system

SystemVerilog 3,561 804 Updated Apr 26, 2026

GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.

C 956 165 Updated Apr 21, 2026

Your Gateway to Embedded Software Development Excellence 👽

Python 9,051 864 Updated Apr 21, 2026

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.

SystemVerilog 285 101 Updated Apr 14, 2026

PicoRV32 - A Size-Optimized RISC-V CPU

Verilog 4,121 939 Updated Jun 27, 2024

RISC-V Cores, SoC platforms and SoCs

920 213 Updated Mar 26, 2021

Build your hardware, easily!

Python 3,850 705 Updated Apr 24, 2026

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

SystemVerilog 1,859 726 Updated Apr 14, 2026

RISC-V: Open-source instruction set architecture based on reduced instruction set computer principles.

350 33 Updated Apr 2, 2026