Skip to content
View heartacker's full-sized avatar
🎯
Focusing
🎯
Focusing

Block or report heartacker

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Starred repositories

13 results for source starred repositories written in Verilog
Clear filter

IC design and development should be faster,simpler and more reliable

Verilog 1,972 591 Updated Dec 31, 2021

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

Verilog 833 204 Updated Apr 15, 2020

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

Verilog 807 278 Updated Sep 23, 2025

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

Verilog 441 206 Updated Jan 29, 2023

iCESugar FPGA Board (base on iCE40UP5k)

Verilog 404 108 Updated Sep 16, 2025

在vscode上的数字设计开发插件

Verilog 388 23 Updated Jan 27, 2023

8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

Verilog 194 51 Updated Oct 9, 2019

iCESugar series FPGA dev board

Verilog 185 28 Updated Sep 16, 2025

CoreScore

Verilog 167 45 Updated Oct 23, 2025

8051 core

Verilog 109 34 Updated Jul 17, 2014

🐥Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.

Verilog 71 28 Updated Nov 22, 2019

FPGA implementation of the 8051 Microcontroller (Verilog)

Verilog 50 15 Updated Sep 27, 2014

iCEstick iCE40-HX1K FPGA hacks ~ iCEfm FM Transmitter

Verilog 18 1 Updated Aug 11, 2017