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RALBot-header Public
Forked from Julian-DD/RALBot-header🪲Generate C/Verilog header file from compiled SystemRDL input
Python UpdatedSep 11, 2025 -
fusesoc Public
Forked from olofk/fusesocPackage manager and build abstraction tool for FPGA/ASIC development
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edalize Public
Forked from olofk/edalizeAn abstraction library for interfacing EDA tools
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cordicio Public
Chisel implementation of a CORDIC design
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pyxsi Public
Forked from gsmecher/pyxsiPython/C/RTL cosimulation with Xilinx's xsim simulator
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symbolator Public
Forked from hdl/symbolatorGenerate symbols from HDL components/modules
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chisel3 Public
Forked from chipsalliance/chiselChisel 3: A Modern Hardware Design Language
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dotfiles Public
My personal configuration files for different applications
Vim Script UpdatedJul 23, 2022 -
pyverilator Public
Forked from csail-csg/pyverilatorPython wrapper for verilator model
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2dconv-FPGA Public archive
A 2D convolution hardware implementation written in Verilog
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MIPS Public
32-bit MIPS Implementation in Verilog
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FCN-car-segmentation Public
A Fully Convolutional Network for car sergmentation
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system-install Public
Personal repository to speed up my ArchLinux system installation
UpdatedJan 19, 2020 -
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redox Public
Forked from redox-os/redoxMirror of https://gitlab.redox-os.org/redox-os/redox
Makefile MIT License UpdatedSep 16, 2019 -
kitty-themes Public
Forked from dexpota/kitty-themesA collection of themes for kitty terminal 😻
Python MIT License UpdatedSep 1, 2019 -
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AppLayer Public
Trabajo Practico n 7 - Redes de Computadoras - FCEFyN UNC
Shell UpdatedJun 21, 2018 -
ElectronicaDigital3-UNC Public
Repositorio para trabajar sobre los codigos de Electronica Digital III
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API-REST-FcefynApp Public
RESTful API using Flask for the FcefynApp project
Python UpdatedJun 26, 2017 -
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