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9 stars written in Verilog
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An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-sp…

Verilog 832 138 Updated Dec 6, 2024

CPU microarchitecture, step by step

Verilog 203 64 Updated Nov 1, 2020

FPGA Logic Analyzer and GUI

Verilog 143 23 Updated Dec 29, 2022

Verilog modules required to get the OV7670 camera working

Verilog 75 35 Updated Jul 26, 2018

USB Full Speed PHY

Verilog 47 8 Updated May 3, 2020

Project: Precise Measure of time delays in FPGA

Verilog 30 13 Updated Aug 3, 2017

USB 1.1 PHY

Verilog 11 8 Updated Jul 17, 2014

Attempt to attach display/mouse/keyboard to VMWAVE virtual machine. HW device for this: Altera MAX10 FPGA dev kit "marsohod3"

Verilog 6 3 Updated Feb 22, 2016

Buildroot on Ebaz4205. How to create from scratch a complete BondMachine accelerated buildroot image for the Ebaz4205 board

Verilog 4 1 Updated Feb 21, 2022