Lists (8)
Stars
4
results
for source starred repositories
written in VHDL
Clear filter
Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom
A Time to Digital Converter designed for Xilinx 7-Series FPGAs
RGB video input for Altera DE1 board + PAL Modulator
Creation of a AXI Master and Yocto device driver for Zynq, using High Level Synthesis (HLS) techniques.