Erasure Code: Extend ec_encode_data_avx2_gfni and ec_encode_data_update_avx2_gfni to support parity blocks k+1 through k+6#423
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1) add 4~6 vector AVX2 dot product with GFNI implementation
2) add AVX2 6vect mad with GFNI implementation
3) ensuring encoding process not modify the input mul_array pointer
Complete the implementations of ec_encode_data_avx2_gfni and
ec_encode_data_update_avx2_gfni to support parity blocks k+1 through
k+6, consistent with the implementations for other instruction sets
(AVX512, AVX2, etc.). This avoids reading source data twice when
computing parities k+4 to k+6, preventing memory bandwidth
amplification.
Signed-off-by: cl304641 <cl304641@alibaba-inc.com>
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|
Hi @OH195-C. I was looking for the question about why there is no p=4,5,6 implementation for AVX2_gfni, as you are implementing it, but I cannot find it... |
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Erasure Code:
1) add 4~6 vector AVX2 dot product with GFNI implementation
2) add AVX2 6vect mad with GFNI implementation
3) ensuring encoding process not modify the input mul_array pointer
Complete the implementations of ec_encode_data_avx2_gfni and ec_encode_data_update_avx2_gfni to support parity blocks k+1 through k+6, consistent with the implementations for other instruction sets (AVX512, AVX2, etc.). This avoids reading source data twice when computing parities k+4 to k+6, preventing memory bandwidth amplification.