A family of hardware priority queue implementations

This is a modified version of the Single-Cycle MIPS processor design from Digital Design and Computer Architecture" (2nd ed.) by David M. Harris and Sarah L. Harris (Morgan-Kaufmann, 2013).

RP2040 Sample Code for ECE 414 at Lafayette College

SystemVerilog examples - common building blocks

VLSI CAD Algorithm Visualizations implemented as Java Applications

FPGA Hardware to control the AdaFruit 16x32 LED Matrix.

Summer Design Projects with Maurice Otieno

Various software implmeentations of priority queues, including a Java implementation of the heap-based priority queue described in Ch. 5 of Cormen, Leiseson, Rivest & Stein

Extended MIPS single-cycle pedagogical design from Harris & Harris "Digital Design and Computer Architecture"

test, check if we can push etc

Shift Register Hardware Priority Queue

Visualization of rectilinear Steiner and Minimum Spanning Trees

Visualization of VLSI Maze Routing Algorithms (Lee, Hadlock, A*)

Animation of VLSI Placement/Floorplanning using Simulated Annealing or Iterative Improvement

A SystemVerilog implementation of Lieserson's Systolic Priority Queue

Register with ready-valid flow control based on Dally & Harting Example 22.1

Hardware Core for Conway's Game of Life

SystemVerilog implementation of Valid-Ready Interface

Tiled Spatial Processing Simulator

L4 Maze Routing Accelerator