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ibex Public
Forked from lowRISC/ibexIbex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
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v7-johnson-demo Public
Turnkey open-source Virtex-7 build: yosys/SVS + nextpnr-xilinx + prjxray + openFPGALoader -> Johnson counter LED demo on VC707
SystemVerilog ISC License UpdatedJun 10, 2026 -
System-Verilog-suite Public
An attempt to convert dumps generated with verilator --json-only back to Verilog
OCaml UpdatedJun 10, 2026 -
sonata-linux Public
A RISCV based linux for sonata-system boards, optimised for 8M hyper ram and 32M serial flash
Makefile UpdatedJun 5, 2026 -
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buildroot Public
Forked from buildroot/buildrootBuildroot, making embedded Linux easy. Note that this is not the official repository, but only a mirror. The official Git repository is at https://gitlab.com/buildroot.org/buildroot/. Do not open i…
Makefile Other UpdatedJun 5, 2026 -
tinyllm-fpga Public
This repo contains System Verilog for running smollm models on the VC707 Xilinx FPGA board
SystemVerilog UpdatedMay 24, 2026 -
prjxray Public
Forked from f4pga/prjxrayDocumenting the Xilinx 7-series bit-stream format.
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OriginSimulator Public
OriginSimulator is an application that provides a dummy telescope for the Celestron Origin App
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OpenROAD-flow-scripts Public
Forked from The-OpenROAD-Project/OpenROAD-flow-scriptsOpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
Verilog Other UpdatedMay 18, 2026 -
cva6 Public
Forked from openhwgroup/cva6The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
Assembly Other UpdatedApr 19, 2026 -
OriginMonitor Public
Provides a Qt App (for macOS initially) that displays the status of your Celestron Origin telescope
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DitherAnalyser Public
Scan a directory of FITS files to verify dither operation
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stellina_processor Public
A simple utility to solve and stack Stellina subframes captured in mosaic mode
C++ UpdatedApr 9, 2026 -
cva6-sdk Public
Forked from openhwgroup/cva6-sdkCVA6 SDK containing RISC-V tools and Buildroot
Makefile GNU General Public License v2.0 UpdatedMar 27, 2026 -
u-boot Public
Forked from openhwgroup/u-bootUnofficial development fork of U-Boot
C UpdatedMar 27, 2026 -
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indi-3rdparty Public
Forked from indilib/indi-3rdpartyINDI 3rd Party drivers repository
C++ GNU Lesser General Public License v2.1 UpdatedMar 18, 2026 -
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tinycc Public
Forked from TinyCC/tinyccExperimental tinycc risvc32 port
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litex-boards Public
Forked from litex-hub/litex-boardsLiteX boards files for sonata
Python BSD 2-Clause "Simplified" License UpdatedMar 12, 2026 -
litespi Public
Forked from litex-hub/litespiSmall footprint and configurable SPI core with >16MB addressing opcodes
Python BSD 2-Clause "Simplified" License UpdatedMar 12, 2026 -
litex Public
Forked from enjoy-digital/litexBuild your hardware, easily! customised for sonata board
C Other UpdatedMar 11, 2026 -
sonata-system Public
Forked from lowRISC/sonata-systemA full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI
C++ Apache License 2.0 UpdatedMar 10, 2026 -
opensbi Public
Forked from litex-hub/opensbiRISC-V Open Source Supervisor Binary Interface
C Other UpdatedMar 10, 2026 -
linux-on-litex-vexriscv Public
Forked from litex-hub/linux-on-litex-vexriscvLinux on LiteX-VexRiscv sonata linux patches
Python BSD 2-Clause "Simplified" License UpdatedMar 10, 2026 -
f4pga-examples Public
Forked from chipsalliance/f4pga-examplesExample designs showing different ways to use F4PGA toolchains.
Verilog Apache License 2.0 UpdatedFeb 1, 2026 -
bytecode Public
An attempt to implement OCaml byte code as a system verilog module (behavioural and RTL versions)
SystemVerilog UpdatedJan 17, 2026 -
Contains core part of the RTS2 - RTS2 libraries, and drivers for basic devices.
C++ GNU Lesser General Public License v3.0 UpdatedJan 8, 2026
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