Skip to content
View kazt81's full-sized avatar
  • QuEL, Inc.
  • Yokohama

Block or report kazt81

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results

This is a FPGA Project on Guitar Effects. Usually, guitarists use one guitar effect Stompbox per effect. This project aimed at using the FPGA hardware, which is significantly faster than Microcontr…

SystemVerilog 7 Updated May 11, 2020

Like VexRiscv, but, Harder, Better, Faster, Stronger

Scala 202 41 Updated Feb 13, 2026
Python 6 3 Updated Dec 26, 2025

The HW-CBMC and EBMC Model Checkers for Verilog

C++ 102 21 Updated Feb 16, 2026

Filelist generator

Ruby 20 1 Updated Feb 3, 2026

Basic Common Modules

SystemVerilog 46 8 Updated Dec 13, 2025
SystemVerilog 11 2 Updated Jan 14, 2026

OpenTitan: Open source silicon root of trust

SystemVerilog 3,139 957 Updated Feb 17, 2026

lowRISC Style Guides

479 128 Updated Nov 6, 2025

SystemVerilog Extension Library -- a library of utilities for generic programming and increased productivity

SystemVerilog 34 6 Updated Jul 27, 2024
SystemVerilog 31 4 Updated Jan 22, 2026
SystemVerilog 117 31 Updated Sep 3, 2024
SystemVerilog 60 31 Updated May 11, 2016

This is the repository for the IEEE version of the book

Verilog 80 48 Updated Sep 29, 2020

Link python model and RTL simulation.

C 5 2 Updated Oct 7, 2014

Enables access from cocotb/Pyuvm to SystemVerilog Verification IP. Besides re-usable code, this repo contains a simple example implementation

Python 2 1 Updated Nov 20, 2024
SystemVerilog 14 3 Updated Jun 7, 2021

CPU assembly examples

Assembly 87 6 Updated May 19, 2024
SystemVerilog 10 2 Updated Nov 2, 2023

auto tb generation for AMS designs . Quickly Build a UVM bench for an arbitrary analog design with external register controls

SystemVerilog 1 Updated Jan 2, 2024

The ROHD Verification Framework is a hardware verification framework built upon ROHD for building testbenches.

Dart 46 13 Updated Oct 7, 2025

Bazel Python Rules

Starlark 1 Updated Jan 4, 2024
Python 37 5 Updated Jul 29, 2024

Develop an embedded Linux system on low-cost Arm based platforms

HTML 184 50 Updated Oct 7, 2025

Implement Digital Signal Processing (DSP) systems and create audio applications using high performance and energy-efficient Arm processors

C 157 51 Updated Oct 7, 2025

Python interface for cross-calling with HDL

Python 47 11 Updated Jan 23, 2026

Veryl: A Modern Hardware Description Language

Rust 885 57 Updated Feb 17, 2026
Verilog 47 6 Updated Jun 4, 2023

ACL2 System and Books as Maintained by the Community

Common Lisp 424 121 Updated Feb 17, 2026
Next