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This is a FPGA Project on Guitar Effects. Usually, guitarists use one guitar effect Stompbox per effect. This project aimed at using the FPGA hardware, which is significantly faster than Microcontr…

SystemVerilog 7 Updated May 11, 2020

Like VexRiscv, but, Harder, Better, Faster, Stronger

Scala 190 38 Updated Dec 19, 2025
Python 6 3 Updated Dec 26, 2025

The HW-CBMC and EBMC Model Checkers for Verilog

C++ 100 20 Updated Dec 30, 2025

Filelist generator

Ruby 20 1 Updated Dec 22, 2025

Basic Common Modules

SystemVerilog 46 8 Updated Dec 13, 2025
SystemVerilog 11 2 Updated Dec 16, 2025

OpenTitan: Open source silicon root of trust

SystemVerilog 3,071 929 Updated Dec 30, 2025

lowRISC Style Guides

473 127 Updated Nov 6, 2025

SystemVerilog Extension Library -- a library of utilities for generic programming and increased productivity

SystemVerilog 33 6 Updated Jul 27, 2024
SystemVerilog 28 4 Updated Jul 29, 2024
SystemVerilog 104 30 Updated Sep 3, 2024
SystemVerilog 58 29 Updated May 11, 2016

This is the repository for the IEEE version of the book

Verilog 77 45 Updated Sep 29, 2020

Link python model and RTL simulation.

C 5 2 Updated Oct 7, 2014

Enables access from cocotb/Pyuvm to SystemVerilog Verification IP. Besides re-usable code, this repo contains a simple example implementation

Python 2 1 Updated Nov 20, 2024
SystemVerilog 12 4 Updated Jun 7, 2021

CPU assembly examples

Assembly 86 5 Updated May 19, 2024
SystemVerilog 10 2 Updated Nov 2, 2023

auto tb generation for AMS designs . Quickly Build a UVM bench for an arbitrary analog design with external register controls

SystemVerilog 1 Updated Jan 2, 2024

The ROHD Verification Framework is a hardware verification framework built upon ROHD for building testbenches.

Dart 46 13 Updated Oct 7, 2025

Bazel Python Rules

Starlark 1 Updated Jan 4, 2024
Python 37 5 Updated Jul 29, 2024

Develop an embedded Linux system on low-cost Arm based platforms

HTML 177 48 Updated Oct 7, 2025

Implement Digital Signal Processing (DSP) systems and create audio applications using high performance and energy-efficient Arm processors

C 150 50 Updated Oct 7, 2025

Python interface for cross-calling with HDL

Python 45 11 Updated Dec 24, 2025

Veryl: A Modern Hardware Description Language

Rust 846 51 Updated Dec 30, 2025
Verilog 47 6 Updated Jun 4, 2023

ACL2 System and Books as Maintained by the Community

Common Lisp 415 119 Updated Dec 30, 2025
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