linien-org · Geosemn · Mar 10, 2026 · Mar 15, 2026 · Mar 15, 2026
diff --git a/dfx_runtime.txt b/dfx_runtime.txt
@@ -0,0 +1,2 @@
+DFXRuntime Profile Report:
+Total Application(DFX) Runtime :                  CPU : 0:0:1 WALL : 0:0:0  0.00 % 
diff --git a/gateware/fpga_image_helper.py b/gateware/fpga_image_helper.py
@@ -69,7 +69,11 @@ def py_csrmap(it, fil):
         fil.write("signals = {}\n".format(repr(root.linien.signal_names)))
 
     platform.add_source_dir(REPO_ROOT_DIR / "gateware" / "verilog")
-    build_dir = REPO_ROOT_DIR / "gateware" / "build"
+    import os
+
+    build_dir = Path(
+        os.environ.get("LIENIEN_BUILD_DIR", str(REPO_ROOT_DIR / "gateware" / "build"))
+    )
     platform.build(root, build_name="top", build_dir=build_dir)
     bit2bin(
         build_dir / "top.bit",

diff --git a/gateware/hw_platform.py b/gateware/hw_platform.py
@@ -14,6 +14,8 @@
 #
 # You should have received a copy of the GNU General Public License
 # along with Linien.  If not, see <http://www.gnu.org/licenses/>.
+import pathlib
+from pathlib import Path
 
 from migen.build.generic_platform import (
     ConstraintError,
@@ -168,9 +170,14 @@ class Platform(XilinxPlatform):
     default_clk_period = 8.0
 
     def __init__(self):
-        XilinxPlatform.__init__(self, "xc7z010-clg400-1", _io, toolchain="vivado")
+        XilinxPlatform.__init__(self, "xc7z020-clg400-1", _io, toolchain="vivado")
+        xdc_path = (
+            pathlib.Path(__file__).resolve().parent
+            / "verilog"
+            / "system_processing_system7_0_0.xdc"
+        )
         self.toolchain.pre_synthesis_commands.append(
-            "read_xdc -ref processing_system7_v5_4_processing_system7 ../verilog/system_processing_system7_0_0.xdc"  # noqa: E501
+            f'read_xdc -ref processing_system7_v5_4_processing_system7 "{xdc_path.as_posix()}"'
         )
         self.toolchain.with_phys_opt = True
 

diff --git a/gateware/linien_module.py b/gateware/linien_module.py
@@ -15,6 +15,8 @@
 # You should have received a copy of the GNU General Public License
 # along with Linien.  If not, see <http://www.gnu.org/licenses/>.
 
+from turtle import width
+
 from linien_common.common import OutputChannel
 from migen import (
     Array,
@@ -56,27 +58,27 @@ def __init__(self, width=14, signal_width=25, chain_factor_width=8, coeff_width=
         self.connect_everything(width, signal_width, coeff_width)
 
     def init_csr(self, width, chain_factor_width):
-        self.dual_channel = CSRStorage(1)
-        self.mod_channel = CSRStorage(1)
-        self.control_channel = CSRStorage(1)
-        self.sweep_channel = CSRStorage(2)
-        self.slow_control_channel = CSRStorage(2)
-        self.pid_only_mode = CSRStorage(1)
+        self.dual_channel = CSRStorage(1, name="dual_channel")
+        self.mod_channel = CSRStorage(1, name="mod_channel")
+        self.control_channel = CSRStorage(1, name="control_channel")
+        self.sweep_channel = CSRStorage(2, name="sweep_channel")
+        self.slow_control_channel = CSRStorage(2, name="slow_control_channel")
+        self.pid_only_mode = CSRStorage(1, name="pid_only_mode")
 
         # we use chain_factor_width + 1 for the single channel mode
         factor_reset = 1 << (chain_factor_width - 1)
-        self.chain_a_factor = CSRStorage(chain_factor_width + 1, reset=factor_reset)
-        self.chain_b_factor = CSRStorage(chain_factor_width + 1, reset=factor_reset)
-        self.chain_a_offset = CSRStorage(width)
-        self.chain_b_offset = CSRStorage(width)
-        self.combined_offset = CSRStorage(width)
+        self.chain_a_factor = CSRStorage(chain_factor_width + 1, reset=factor_reset, name="chain_a_factor")
+        self.chain_b_factor = CSRStorage(chain_factor_width + 1, reset=factor_reset, name="chain_b_factor")
+        self.chain_a_offset = CSRStorage(width, name="chain_a_offset")
+        self.chain_b_offset = CSRStorage(width, name="chain_b_offset")
+        self.combined_offset = CSRStorage(width, name="combined_offset")
         self.combined_offset_signed = Signal((width, True))
-        self.out_offset = CSRStorage(width)
-        self.slow_decimation = CSRStorage(bits_for(16))
+        self.out_offset = CSRStorage(width, name="out_offset")
+        self.slow_decimation = CSRStorage(bits_for(16), name="slow_decimation")
         for i in range(1, 4):
             setattr(self, f"analog_out_{i}", CSRStorage(15, name=f"analog_out_{i}"))
 
-        self.slow_value = CSRStatus(width)
+        self.slow_value = CSRStatus(width, name="slow_value")
 
         self.chain_a_offset_signed = Signal((width, True))
         self.chain_b_offset_signed = Signal((width, True))
@@ -211,7 +213,7 @@ def init_submodules(
         sys_double = ClockDomainsRenamer("sys_double")
         max_decimation = 16
         self.submodules.decimate = sys_double(Decimate(max_decimation))
-        self.clock_domains.cd_decimated_clock = ClockDomain()
+        self.clock_domains.cd_decimated_clock = ClockDomain("decimated_clock")
         decimated_clock = ClockDomainsRenamer("decimated_clock")
         self.submodules.slow_chain = decimated_clock(SlowChain())
 
@@ -414,7 +416,7 @@ def connect_everything(self, width, signal_width, coeff_width, chain_factor_bits
 
 class DummyID(Module, AutoCSR):
     def __init__(self):
-        self.id = CSRStatus(1, reset=1)
+        self.id = CSRStatus(1, reset=1, name="id")
 
 
 class DummyHK(Module, AutoCSR):

diff --git a/gateware/logic/autolock.py b/gateware/logic/autolock.py
@@ -39,9 +39,9 @@ def __init__(self, width=14, N_points=16383, max_delay=16383):
 
         self.submodules.fast = SimpleAutolock(width=width)
 
-        self.request_lock = CSRStorage()
-        self.autolock_mode = CSRStorage(2)
-        self.lock_running = CSRStatus()
+        self.request_lock = CSRStorage( name = "request_lock")
+        self.autolock_mode = CSRStorage(2, name = "autolock_mode")
+        self.lock_running = CSRStatus(name= "lock_running")
 
         self.comb += [
             self.fast.request_lock.eq(self.request_lock.storage),
@@ -85,7 +85,7 @@ def __init__(self, width=14):
         self.sweep_step = Signal(width)
         self.sweep_up = Signal()
 
-        self.target_position = CSRStorage(width)
+        self.target_position = CSRStorage(width, name = "target_position")
         target_position_signed = Signal((width, True))
 
         self.comb += [target_position_signed.eq(self.target_position.storage)]
@@ -240,9 +240,9 @@ def init_submodules(self, width, N_points, max_delay):
 
     def init_csr(self, N_points):
         # CSR storages
-        self.time_scale = CSRStorage(bits_for(N_points))
-        self.N_instructions = CSRStorage(bits_for(AUTOLOCK_MAX_N_INSTRUCTIONS - 1))
-        self.final_wait_time = CSRStorage(bits_for(N_points))
+        self.time_scale = CSRStorage(bits_for(N_points), name = "time_scale")
+        self.N_instructions = CSRStorage(bits_for(AUTOLOCK_MAX_N_INSTRUCTIONS - 1), name = "N_instructions")
+        self.final_wait_time = CSRStorage(bits_for(N_points), name = "final_wait_time")
 
         peak_height_bit = len(self.sum_diff_calculator.sum_value)
         self.peak_heights = [

diff --git a/gateware/logic/chains.py b/gateware/logic/chains.py
@@ -34,8 +34,8 @@ def __init__(
         # output of quadrature demodulated signal
         self.out_q = Signal((signal_width, True))
 
-        self.y_tap = CSRStorage(2)
-        self.invert = CSRStorage(1)
+        self.y_tap = CSRStorage(2,name= "y_tap")
+        self.invert = CSRStorage(1,name= "invert")
 
         self.state_in = []
         self.state_out = []
@@ -162,8 +162,8 @@ def cross_connect(gpio, chains):
     states = Cat(states)
     state = Signal(len(states))
     gpio.comb += state.eq(states)
-    gpio.state = CSRStatus(len(state))
-    gpio.state_clr = CSR()
+    gpio.state = CSRStatus(len(state), name="state")
+    gpio.state_clr = CSR(name="state_clr")
     gpio.sync += [
         If(
             gpio.state_clr.re,

diff --git a/gateware/logic/iir.py b/gateware/logic/iir.py
@@ -38,13 +38,13 @@ def __init__(
             intermediate_width = width + coeff_width
             # + bits_for(2*(order + 1))
 
-        self.z0 = CSRStorage(intermediate_width - shift, reset=0)
-        self.shift = CSRConstant(shift)
-        self.width = CSRConstant(coeff_width)
-        self.interval = CSRConstant(0, 8)
-        self.latency = CSRConstant(0, 8)
-        self.order = CSRConstant(order, 8)
-        self.iterative = CSRConstant(mode == "iterative", 1)
+        self.z0 = CSRStorage(intermediate_width - shift, reset=0, name = "z0")
+        self.shift = CSRConstant(shift, name = "shift")
+        self.width = CSRConstant(coeff_width, name = "width")
+        self.interval = CSRConstant(0, 8, name = "interval")
+        self.latency = CSRConstant(0, 8, name = "latency")
+        self.order = CSRConstant(order, 8, name = "order")
+        self.iterative = CSRConstant(mode == "iterative", 1, name = "iterative")
 
         self.c = c = {}
         for i in "ab":

diff --git a/gateware/logic/limit.py b/gateware/logic/limit.py
@@ -56,8 +56,8 @@ def __init__(self, guard=0, **kwargs):
         width = len(self.y)
         if guard:
             self.x = Signal((width + guard, True))
-        self.min = CSRStorage(width, reset=1 << (width - 1))
-        self.max = CSRStorage(width, reset=(1 << (width - 1)) - 1)
+        self.min = CSRStorage(width, reset=1 << (width - 1), name = "min")
+        self.max = CSRStorage(width, reset=(1 << (width - 1)) - 1, name = "max")
 
         ###
 

diff --git a/gateware/logic/modulate.py b/gateware/logic/modulate.py
@@ -31,8 +31,8 @@ def __init__(self, freq_width=32, width=14):
         self.i = Signal((width, True))
         self.q = Signal((width, True))
 
-        self.delay = CSRStorage(freq_width)
-        self.multiplier = CSRStorage(4, reset=1)
+        self.delay = CSRStorage(freq_width, name="delay")
+        self.multiplier = CSRStorage(4, reset=1, name="multiplier")
         self.phase = Signal(width)
 
         self.submodules.cordic = Cordic(
@@ -60,8 +60,8 @@ def __init__(self, freq_width=32, **kwargs):
         Filter.__init__(self, **kwargs)
 
         width = len(self.y)
-        self.amp = CSRStorage(width)
-        self.freq = CSRStorage(freq_width)
+        self.amp = CSRStorage(width, name="amp")
+        self.freq = CSRStorage(freq_width, name="freq")
         self.phase = Signal(width)
 
         self.sync_phase = Signal()

diff --git a/gateware/logic/pid.py b/gateware/logic/pid.py
@@ -37,7 +37,7 @@ def __init__(self, width=14, coeff_width=14):
         self.calculate_sum()
 
     def calculate_error_signal(self):
-        self.setpoint = CSRStorage(self.width)
+        self.setpoint = CSRStorage(self.width, name ="setpoint")
         setpoint_signed = Signal((self.width, True))
         self.comb += [setpoint_signed.eq(self.setpoint.storage)]
 
@@ -50,7 +50,7 @@ def calculate_error_signal(self):
         ]
 
     def calculate_p(self):
-        self.kp = CSRStorage(self.coeff_width)
+        self.kp = CSRStorage(self.coeff_width, name = "kp")
         kp_signed = Signal((self.coeff_width, True))
         self.comb += [kp_signed.eq(self.kp.storage)]
 
@@ -63,8 +63,8 @@ def calculate_p(self):
         self.kp_mult = kp_mult
 
     def calculate_i(self):
-        self.ki = CSRStorage(self.coeff_width)
-        self.reset = CSRStorage()
+        self.ki = CSRStorage(self.coeff_width, name = "ki")
+        self.reset = CSRStorage(name = "reset")
 
         ki_signed = Signal((self.coeff_width, True))
         self.comb += [ki_signed.eq(self.ki.storage)]
@@ -106,7 +106,7 @@ def calculate_d(self):
         mult_width = self.coeff_width + self.width + 2
         out_width = mult_width - self.coeff_width + self.d_shift + 1
 
-        self.kd = CSRStorage(self.coeff_width)
+        self.kd = CSRStorage(self.coeff_width, name = "kd")
         kd_signed = Signal((self.coeff_width, True))
         kd_mult = Signal((mult_width, True))
 

diff --git a/gateware/logic/sweep.py b/gateware/logic/sweep.py
@@ -69,11 +69,11 @@ def __init__(self, width, step_width=None, step_shift=0):
         if step_width is None:
             step_width = width
 
-        self.step = CSRStorage(step_width)
-        self.min = CSRStorage(width, reset=1 << (width - 1))
-        self.max = CSRStorage(width, reset=(1 << (width - 1)) - 1)
-        self.run = CSRStorage(1)
-        self.pause = CSRStorage(1)
+        self.step = CSRStorage(step_width, name ="step")
+        self.min = CSRStorage(width, reset=1 << (width - 1), name="min")
+        self.max = CSRStorage(width, reset=(1 << (width - 1)) - 1, name="max")
+        self.run = CSRStorage(1, name="run")
+        self.pause = CSRStorage(1, name="pause")
 
         ###
 

diff --git a/gateware/lowlevel/crg.py b/gateware/lowlevel/crg.py
@@ -20,11 +20,11 @@
 
 class CRG(Module):
     def __init__(self, clk_adc, clk_ps, rst):
-        self.clock_domains.cd_sys_quad = ClockDomain(reset_less=True)
-        self.clock_domains.cd_sys_double = ClockDomain(reset_less=True)
-        self.clock_domains.cd_sys = ClockDomain()
-        self.clock_domains.cd_sys_slow = ClockDomain(reset_less=True)
-        self.clock_domains.cd_sys_ps = ClockDomain()
+        self.clock_domains.cd_sys_quad = ClockDomain("sys_quad", reset_less=True)
+        self.clock_domains.cd_sys_double = ClockDomain("sys_double", reset_less=True)
+        self.clock_domains.cd_sys = ClockDomain("sys")
+        self.clock_domains.cd_sys_slow = ClockDomain("sys_slow", reset_less=True)
+        self.clock_domains.cd_sys_ps = ClockDomain("sys_ps")
         self.comb += [self.cd_sys_ps.clk.eq(clk_ps), self.cd_sys_ps.rst.eq(rst)]
 
         clk_adci = Signal()

diff --git a/gateware/lowlevel/dna.py b/gateware/lowlevel/dna.py
@@ -22,7 +22,7 @@
 class DNA(Module, AutoCSR):
     def __init__(self, version=0b1000001):
         n = 64
-        self.dna = CSRStatus(n, reset=version << 57)
+        self.dna = CSRStatus(n, reset=version << 57, name = "dna")
 
         ###
 

diff --git a/gateware/lowlevel/gpio.py b/gateware/lowlevel/gpio.py
@@ -25,9 +25,9 @@ def __init__(self, pins):
         n = len(pins)
         self.i = Signal(n)
         self.o = Signal(n)
-        self.ins = CSRStatus(n)
-        self.outs = CSRStorage(n)
-        self.oes = CSRStorage(n)
+        self.ins = CSRStatus(n, name = "ins")
+        self.outs = CSRStorage(n, name = "outs")
+        self.oes = CSRStorage(n, name = "oes")
 
         ###
 

diff --git a/gateware/lowlevel/scopegen.py b/gateware/lowlevel/scopegen.py
@@ -47,7 +47,7 @@ def __init__(self, width=25):
             ).Else(automatic_trigger_signal.eq(0))
         ]
 
-        self.external_trigger = CSRStorage(1)
+        self.external_trigger = CSRStorage(1,name="external_trigger")
         ext_scope_trigger = Array([self.gpio_trigger, self.sweep_trigger])[
             self.external_trigger.storage
         ]

diff --git a/gateware/lowlevel/xadc.py b/gateware/lowlevel/xadc.py
@@ -35,12 +35,12 @@ def __init__(self, xadc):
         self.ot = Signal()
         self.adc = [Signal((12, True)) for i in range(4)]
 
-        self.temp = CSRStatus(12)
-        self.v = CSRStatus(12)
-        self.a = CSRStatus(12)
-        self.b = CSRStatus(12)
-        self.c = CSRStatus(12)
-        self.d = CSRStatus(12)
+        self.temp = CSRStatus(12, name = "temp")
+        self.v = CSRStatus(12, name = "v")
+        self.a = CSRStatus(12, name = "a")
+        self.b = CSRStatus(12, name = "b")
+        self.c = CSRStatus(12, name = "c")
+        self.d = CSRStatus(12, name = "d")
 
         ###
Original file line number	Diff line number	Diff line change
		@@ -0,0 +1,2 @@
		DFXRuntime Profile Report:
		Total Application(DFX) Runtime : CPU : 0:0:1 WALL : 0:0:0 0.00 %