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19 followers · 11 following
  • USTC
  • Hefei, China

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louvinci/README.md
  • 👋 Hi, I’m louvinci, a phd student in USTC
  • 👀 I’m interested in FPGA accelerator design and neural network compression algorithm
  • 🌱 I’m currently learning DNN/Accelerator Co-design
  • 🧰 languages: C, HLS, Python, Verilog
  • ⚡ tools: Pytorch and Vitis

Pinned Loading

  1. vitis_workflow_yunji vitis_workflow_yunji Public

    Forked from YunjiQin/vitis_workflow

  2. PACT-Quantization PACT-Quantization Public

    Quantization (QAT) Demo on CIFAR10

    Python 17 1

  3. HLStoFPGA HLStoFPGA Public

    ZCU104, Vitis, Tutorial

    C 3

  4. BlockPU BlockPU Public

    DW+PW+PW hls core

    C++ 3

  5. Deploy_FFT_Vitis_demo Deploy_FFT_Vitis_demo Public

    C++ 1 1

  6. ViT-Accelerator-on-FPGA-with-INT8-quantization ViT-Accelerator-on-FPGA-with-INT8-quantization Public

    Jupyter Notebook 6