Introduction to Machine Learning Systems

Windows inside a Docker container.

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Keystone Enclave (QEMU + HiFive Unleashed)

Ghidra is a software reverse engineering (SRE) framework

Penglai Enclave is an open-sourced, secure and scalable TEE system for RISC-V.

🎧 Web page for listen combinations of sounds for relax, sleep, or getting more productive on tasks.

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original Zero-RI5CY work from ETH Zurich and Ibex work from lowRISC.

Bare metal Raspberry Pi 3 tutorials

RISC-V Security HC admin repo

Build your hardware, easily!

This repo holds the work area and revisions of the RISC-V CFI (Shadow Stack and Landing Pads) specifications. CFI defines the privileged and unprivileged ISA extensions that can be used by privileg…

An optimized neural network operator library for chips base on Xuantie CPU.

Bootlin embedded Linux and kernel training materials