Adc3 support#9594
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Enables ADC3 as a second slow ADC bank on STM32F7 (and similar) targets that define ADC3_SLOW_CHANNEL_COUNT. Adds background-mode callback (slowAdc3EndCB), updates the state machine to interleave ADC3 primary and muxed passes alongside ADC1, and introduces ADC_MUX_PIN_INVERTED to support boards where the mux select polarity is reversed. SLOW_ADC_CHANNEL_COUNT in adc_onchip_slow.cpp is updated to account for the extra ADC3 primary + muxed channels when the macro is defined. EFI_ADC_40+ comment clarified to reflect muxed ADC3 usage. Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
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| #ifdef ADC3_SLOW_CHANNEL_COUNT | ||
| static void slowAdc3EndCB(ADCDriver *adcp) { |
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Is there any chance to use same slowAdcEndCB for both ADC?
So whole state machine will be in one place easy to read and maintain.
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I will be implementing this and testing to see if nothing breaks
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poke @ElDominio |
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Have not been able to go to shop, should be tested tomorrow |
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Tested in car, working for adc channels on adc3 |
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@ElDominio can you attempt a (new?) clean PR without libfirmware and merge commits? |
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will be happening today! |
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let's keep this one open until a better one exists, just in case? |
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exploded on proteus_f4 and 8chan f4; master is doing this too; what is the course of action? in my locals i have set 8chan f4 to not comple inis or wideband firmware on board because space |
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@ElDominio can you attempt a (new?) clean PR without libfirmware and merge commits? |
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I was going to PR, but I got a hunch that something was still up, and talking with my new buddy Antigravity sort of confirmed something. I had not taken time to consider that if we enable ADC3 muxing, the system could possibly also try to mux ADC1. Antigravity said so i will be trying to debug this before PR |
this adds support to have mux channels on adc3, since my s550 board was made with PF analog inputs on STM32F7, and they are muxed. I have tested this on the board and the mux inputs work