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open-logic Public
Forked from open-logic/open-logicOpen Logic FPGA Standard Library
VHDL Other UpdatedJan 1, 2026 -
fusesoc-generators Public
Forked from fusesoc/fusesoc-generatorsA collection of core generators to use with FuseSoC
Python MIT License UpdatedDec 18, 2025 -
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cocotb-test Public
Forked from themperek/cocotb-testUnit testing for cocotb
Python BSD 2-Clause "Simplified" License UpdatedDec 6, 2025 -
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edalize Public
Forked from olofk/edalizeAn abstraction library for interfacing EDA tools
Python BSD 2-Clause "Simplified" License UpdatedOct 6, 2025 -
fusesoc Public
Forked from olofk/fusesocPackage manager and build abstraction tool for FPGA/ASIC development
Python BSD 2-Clause "Simplified" License UpdatedOct 6, 2025 -
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synthesis-primitives Public
Forked from jeras/synthesis-primitivesObserving and optimizing synthesis of common bit manipulation operations for FPGA and ASIC
SystemVerilog UpdatedJan 19, 2025 -
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fusesoc-cores Public
Forked from fusesoc/fusesoc-coresFuseSoC standard core library
UpdatedDec 26, 2024 -
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vunit Public
Forked from VUnit/vunitVUnit is a unit testing framework for VHDL/SystemVerilog
VHDL Other UpdatedDec 21, 2024 -
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surf-fork Public
Forked from slaclab/surfA huge VHDL library for FPGA development
VHDL Other UpdatedDec 1, 2024 -
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ruckus Public
Mirror of SLAC ruckus: https://github.com/slaclab/ruckus
Tcl Other UpdatedNov 18, 2024 -
VHDL 2008/93/87 simulator
VHDL GNU General Public License v2.0 UpdatedJan 1, 2024 -
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stm32-mastering_mcu2 Public
Following udemy tutorial : https://www.udemy.com/course/microcontroller-programming-stm32-timers-pwm-can-bus-protocol/
C UpdatedJul 16, 2023 -