My simple personal website

Collection of utility modules written in Verilog

for photos etc.

Simple command line truth or dare game written in python

Repository for my bash scripts

Collection of exercises to learn rust

Config files for my GitHub profile.

Set of simple modules to communicate using SPI protocol.

Pseudorandom number generator

Set of simple modules to communicate via UART

Simple queue management system

Collection of simple interfaces for Digilent Pmods

Simple interface for MCP9808 temperature sensor

Interface module for MCP4725 DAC

Encoder and decoder modules for infrared receivers, transmitters and remotes

Simple I²S Master

Set of simple modules to communicate via I²C Bus.

Verilog interface for HC-SR04 Ultrasonic Ranging Module

16-bit Adder Multiplier hardware on Digilent Basys 3

Hardware integer divider module

Verilog code for a digital clock

Pair of modules to calculate crc values sequentially

Slaves for AXI-lite interface

Splits one AXI-Stream transmission to two.

AXIS buffer to keep data until next stage accepts it. Does not add any latency.

Custom AXI GPIO core with up to 32 input and 32 output ports

Simple script to convert images to BMP files or raw RGB binary file.

Combinational adder and multiplier modules for IEEE 754 single-precision and double-precision floating point format.

Some snippets for Verilog HDL to be used in VS Code

Serial communication tool written in Python 3