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Commits on Aug 9, 2026

• Merge pull request #140 from sdrangan/firblock-vitis-model

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• docs(firblock): the DSP cancellation table becomes a real table

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• docs(firblock): table lists the parameters, not the key or the entry counts

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• docs(firblock): lead with the module table, and say what each lookup keys on

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• docs(firblock): reorganise resource_model.md around the declaration

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• docs(firblock): resource pages follow the vecmult shape

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• test: follow fir_block's migration, and check the declaration against the oracle

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• refactor(fir_block): FirCompute on a stock VitisResourceModel

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Commits on Aug 8, 2026

• Merge pull request #139 from sdrangan/resource-model-section

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• docs(resource_model): restructure the section around what a user writes

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• test: follow the new declaration, and catch one more form of eaten space

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• refactor(vecmult): a stock model, no subclass and no hand-built sample list

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• refactor(calib): InterfaceResourceModel is a lookup keyed on the boundary

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• feat(calib): write the LUT/FF basis directly, and hold the counted part out

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• feat(calib): price LUTRAM-bound storage with a device rule

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Commits on Aug 6, 2026

• Merge pull request #138 from sdrangan/docs-guide-toc

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• docs(examples): generated TOC, a summary per example, and one naming convention

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• docs(guide): drop the hand-written section list, and summarise every section

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• docs(guide): rename Resource analysis -> Resource Analysis Tools, beside Timing

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• Merge pull request #137 from sdrangan/docs-vecmult-implementation

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• docs(vecmult): record why vec_cls cannot simply be deleted

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• docs(vecmult): add the two codegen pages

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• docs(vecmult): the multiply, the golden, and what the pages elided

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Commits on Aug 5, 2026

• Merge pull request #136 from sdrangan/fix-rtlsim-tb-dependency

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• plans(sweep_runner): the mem_copy stall was a missing DAG edge, not RTL

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• fix(trace): rtlsim depends on the testbench it compiles

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• plans(sweep_runner): the mem_copy stall has no simple invariant — stop probing, instrument

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• plans(sweep_runner): the n=1024 stall is a VOLUME ceiling, not a job-count one

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• Merge branch 'sweep-runner': one sweep runner for both calibration axes

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• feat(sweep): Stage.barrier, and mem_copy calibrates its bus law before its writer

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• fix(trace): refuse a firing table that is short, and stop guessing why

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• plans(sweep_runner): P3b done — Stage serves timing, and two defects it found

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• feat(sweep): Stage.force, and mem_copy's timing sweep reproduces its constants

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• fix(trace): the manifest names a task by its CONFIGURATION, not its function

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• feat(mem_copy): wire the timing calibration rung into the build DAG

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