Digital clock implemented in vhdl for the Basys 3 Board from Digilent.

A 16-bit MIPS cpu in VHDL

Controle de motor DC + Sensores fim de curso implementado em VHDL para o kit DE0-CV utilizado na matéria de Elementos de sistemas do 3 semestre de Engenharia da computação do Insper.

NEANDER - A basic theorical computer

A repository for showcasing my knowledge of the VHDL programming language, and continuing to learn the language.

This repository is dedicated to storing and managing homework assignments for the course "Digital Circuit Design: Modeling and Description Languages." The assignments primarily involve VHDL source code.

Circuito de controle de sala de reuniões implementado em VHDL

Trabalhos, Projetos, Exercícios e aulas realizados em VHDL e Assembly na cadeira de Fundamentos de sistemas digitais, matéria do segundo semestre.

Computer organisation and architecture assignments

My first attempt with VHDL/FPGA technology (including hardware test on Red Pitaya). 📊

VHDL source code implementing the insertion sort algorithm on a DP32.

Лабораторные работы по предмету "Языки моделирования и описания цифровой аппаратуры" (универ, 3-ий семестр)

Scripts VHDL pour le cours Logique des systèmes numériques (INF1500) de Polytechnique Montréal

FPGAs in VHDL

FSM for controlling RGB LEDs on an FPGA board (VHDL)

Σκοπός είναι η σχεδίαση και υλοποίηση του επεξεργαστή MIPS απλού κύκλου. Ο επεξεργαστής έχει ως είσοδο τα σήματα reset και clock, ενώ δεν έχει έξοδο. Το σήμα reset οδηγεί τη μονάδα PC στην τιμή 0. Επίσης οδηγεί το Register file και μηδενίζει όλους τους καταχωρητές.

An logic analyser built on a FPGA with VGA outptut.