Prepositional logic solver

Projects for the Nexys A7 FPGA development board

A 32-bit MIPS processor implemented in VHDL, supporting basic instructions (R, I, and J-type). Designed and simulated using ModelSim. Implements instruction fetch, decode, execute, memory access, and write-back stages.

Este projeto implementa um relógio de xadrez utilizando a linguagem VHDL. O sistema gerencia o tempo de jogo de dois jogadores e exibe os tempos restantes em um display.

A real-time FPGA-based smart gas metering and safety system built in Verilog HDL and implemented in Xilinx Vivado for the Digilent Basys3 (Artix-7) board. The project combines gas leakage detection, audio-visual alerting, prepaid gas credit management, password-protected recharge, and live status display on a 7-segment interface.

A 4-bit ripple-carry adder and a 4-bit register using Verilog HDL on a Basys-3 FPGA.

Counter– Registru Paralel