Machine learning on FPGAs using HLS
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Updated
Jun 10, 2026 - Python
Machine learning on FPGAs using HLS
An abstraction library for interfacing EDA tools
Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
A flexible and scalable development platform for modern FPGA projects.
HDLGen-ChatGPT, works in tandem with ChatGPT chat interface to enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testbenches, and AMD Vivado and Intel Quartus Electronic Design Automation (EDA) project
Bazel rules for Xilinx Vivado
Example of how to get started with olofk/fusesoc.
Resource Utilization and Latency Estimation for ML on FPGA.
Simulation and implementation flow for hardware description languages
Visual System Integrator - Accelerate your embedded development
This project automates process of creating a PYNQ Z1/Z2 Overlay in Vivado, generates a custom Juypter Notebook template and uploads to a target PYNQ FPGA.
CLI + Claude Code skill to capture and analyze Vivado ILA waveforms without leaving your editor
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