parity calculator for the given bit stream

Verilog UART implementation with Vivado build scripts to test loopback on Xilinx Arty board

Chipathon GF180MCU LibreLane examples: 5 hands-on notebooks (counter bare-block, chip-top with macro, workshop slot use, multi-macro counter+ALU) for the chipathon-2026-gf180mcu-padring fork.

Full RTL-to-GDSII implementation of an 8-bit registered adder using SkyWater 130nm PDK and open-source EDA tools

This repository provides a lightweight, scalable automated verification pipeline for VHDL-based designs. It integrates GHDL (simulation) and Cocotb (Python-based verification) into GitHub Actions, ensuring that every code change is automatically validated.

Simple personal tooling for quickly bootstrapping hardware development projects using open-source tools (Verilator, cocotb, TOML-based configuration)

Implementation of a RISC-V CPU in SystemVerilog.

A complete FIR filter design suite: VHDL hardware implementation

DMA Controller for the transfer of 8-bit words between Memory and I/O Device. Hardening through LibreLane using SKY130 PDK. Submitted to the SKY26b TinyTapeout Shuttle

This repository contains some starting example for verifying RTL using CocoTB.

mostly simple VHDL stuff

Offset, Leading Zero detector

This project implements the SHA-256 cryptographic hash function in Verilog. It includes a modular design with separate modules for various components, as well as testbenches written in Python using Cocotb for simulation and verification.

Common SystemVerilog modules I use in my FPGA projects

mirror of https://git.elphel.com/Elphel/oc_jpegencode_vdt