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clock-domain-crossing
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In digital design, it is sometimes necessary to transfer data from one clock domain to another. However because of the nature of how data is stored, there is a probability the transaction will have a setup and hold violation or data is lost because of the different between the domain speeds.
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Nov 20, 2020 - VHDL
A Fault Tolerant Globally-Asynchronous-Locally-Synchronous Inter-Chip Communication Bridge on FPGAs
fpga communication-protocol asynchronous embedded-systems fault-tolerant fault-detection network-on-chip interchip-bridge clock-domain-crossing
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Oct 30, 2017 - VHDL
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