open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

Guilde how to create custom DMA firmware.

A Direct Memory Access Controller (DMAC) with AHB-lite bus interface

Hardware accelerator for 2D convolution using an 8×8 weight-stationary systolic array with split-kernel support, dual-port SRAM architecture, and DMA-based streaming

一个基于AXI的DMA

FIFO and DMA combination study - "CY8C5888AXI-LP096" on "FreeSoC2"

A high performance DMA subsystem using AXI4 Full protocols and a custom 16 bank eDRAM architecture. Designed for maximum throughput and minimal leakage, it features predictive bank wakeup logic and deterministic timing closure at 100MHz.

Build an open source, extremely simple DMA.