ISTD 50.002 Computation Structures Beta CPU [SUTD]

Interactive memory game implemented in Verilog and deployed on Nexys-A7 FPGA using FSM-based logic.

HDL Bits solution

This project is a fully automated parking control system implemented using an HDL (Hardware Description Language), more specificaly Verilog. The system is designed to efficiently manage access of vehicles, requesting password and controlling the parking gate arm with the help of sensors.

Verilog implementation of native Brainfuck CPU

FSM: Sequence Detector using Verilog HDL

Collection of the solutions to HDL Bits Problem Sets

::Alphanumeric custom messages on 8 x 7-segment displays with integrated 4 button menu.

Solutions to Mr. Foshati's CE223: Digital System Design Course (Sharif University of Technology - Spring 2025)

Code for Computer Architecture Lab

Reusable Verilog Components

Repo for my projects for Computer System Design Class

Implementing a Multimodal clock in Verilog using FPGA

A dedicated Verilog HDL practice space focused on designing, simulating, and documenting digital logic circuits using Xilinx Vivado. This repository aims to strengthen HDL fundamentals through clean code, structured testbenches, and visual outputs like schematics and timing diagrams.

VLSI mini projects using verilog with source code

This contains my solution to the labs of Computer Architecture course for the year 2020-21

a command-line tool for automatic judge of verilog HDL code.

Anton's "Simple Multiply" submission for Tiny Tapeout 3 (TT03)

Important Verilog codes for both combinational and sequential circuits. Look into and explore!