Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.
HDL Bits solution
This project is a fully automated parking control system implemented using an HDL (Hardware Description Language), more specificaly Verilog. The system is designed to efficiently manage access of vehicles, requesting password and controlling the parking gate arm with the help of sensors.
Timing reports are generated for various circuits using an open source tool OpenSTA. Both min and max timing reports are generated. The commands are given using a tcl script and I have used a 45nm pdk for technology mapping. The circuit is described using Verilog language. We can also generate or report power dissipated by design. MMMC is performed
Verilog implementation of native Brainfuck CPU
Collection of the solutions to HDL Bits Problem Sets
::Alphanumeric custom messages on 8 x 7-segment displays with integrated 4 button menu.
VLSI mini projects using verilog with source code
A dedicated Verilog HDL practice space focused on designing, simulating, and documenting digital logic circuits using Xilinx Vivado. This repository aims to strengthen HDL fundamentals through clean code, structured testbenches, and visual outputs like schematics and timing diagrams.
This contains my solution to the labs of Computer Architecture course for the year 2020-21
Anton's "Simple Multiply" submission for Tiny Tapeout 3 (TT03)
Important Verilog codes for both combinational and sequential circuits. Look into and explore!
This repository provides a parameterized hardware implementation of a Posit Arithmetic Unit (PAU) written in Verilog. It supports addition, subtraction, multiplication, and division over configurable posit formats, and includes a full verification framework using a C++ golden reference model.
An efficient multi-format low-precision floating-point multiplier