RISCV processor done in both single cycle and pipeline (with CSR support) form.

Implementing a 32-bit processor using RISC-V architecture.

Reproduction of the HiVeGen (Hierarchical LLM-based Verilog Generation) pipeline from the paper "HiVeGen – Hierarchical LLM-based Verilog Generation for Scalable Chip Design" (arXiv:2412.05393).

SystemVerilog IP AUDIY originally designed.

Roteiros desenvolvidos na disciplina de Laboratório de Organização e Arquitetura de Computadores no período 2022.2

Digital hardware designs for flightless birds

Implementation of 3 stage pipelined processor based on RISC-V Instruction Set Architecture

Old noob practice stuff (Incomplete due to broken network; Will complete repo later. Also ignore commit messages)

Verilog implementation of a traffic light Finite State Machine (FSM).

ZX Spectrum implementation for maximator board

Algoritmos de descrição de hardware feitos em SystemVerilog durante as aulas de ANÁLISE DE CIRCUITOS DIGITAIS II, do 8° semestre do curso de Engenharia de Computação - SETREM.

Group 8 ECE271 final term project. NES controller deconder with PS/2 keyboard decoder.

This repository contains SystemVerilog code examples for beginners.

Digital Circuit Design with the SystemVerilog Hardware Description Language (HDL). Digital Circuits will then be synthesised on an FPGA.

A SystemVerilog-based UART (Universal Asynchronous Receiver/Transmitter) module built from scratch using FSM design. Includes baud tick generator, transmitter and receiver FSMs, and simulation testbenches for 8N1 serial communication.

For finalizing experimental development work on the mksocfpga_hm3 repo back into machinekit

Basic Stopwatch Design using Terasic DE-10 Standard FPGA

This repository will host slides and support code for the webinar "Latency Insensitive Design: Theoretical and Practical Considerations".

A 480p (VGA) 16 bit sprite rendering processing unit