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hdl

Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.

Here are 66 public repositories matching this topic...

franos-cm / dilithium-comparison

Comparison between two RTL designs that fully implement the CRYSTALS-Dilithium algorithm

hdl hardware-acceleration dilithium crystals-dilithium

Updated Aug 7, 2025
VHDL

tharaka27 / Hardware-Description-Languages-for-FPGA-Design

Hardware Description Languages for FPGA Design by University of Colorado Boulder

embedded fpga vhdl coursera hdl

Updated Aug 16, 2020
VHDL

daniel-deiana / 2D-Convolution-VHDL

2D Convolution FPGA Accelerator in VHDL

fpga vhdl convolution hdl

Updated Aug 30, 2023
VHDL

Pauls-University-Projects / VHDL-Counter

Year 2 - Analogue and Digital Electronics 2 (201CDE) Project

counter university vhdl synchronous sequential hdl coventry-university 201cde

Updated May 12, 2021
VHDL

MohammedS2lah / Digital_Design_With_VHDL

In this repository, I'll provide a simple, organized collection of VHDL designs and tutorials to help anyone learn and practice digital design using VHDL.

vhdl hardware-designs hdl vhdl-modules hardware-description-language vhdl-code vhdl-examples vhdl-testbench hardware-design vhdl-language

Updated Jan 24, 2025
VHDL

AlexNoodle0127 / Intel4004Clone

This file contains a work-in-progress Intel4004 Clones as well as a Readme discussing my post-Von Neumann idea of what computing can be.

vhdl hdl symbolic-computation cpu-design intel4004 meta-architecture post-von-neumann

Updated Nov 5, 2025
VHDL

ChaminduS / HDL-for-FPGA

This repository contains the resources for my ongoing course 'HDL for FPGA design' through Coursera

fpga vhdl verilog hdl

Updated Dec 16, 2021
VHDL

AmitKharade82 / VHDL

vhdl vivado hdl vlsi

Updated Jun 10, 2021
VHDL

PeterAyad / Verilog-VHDL-Examples

The Verilog And VHDL Examples I Made When I Was An Undergraduate Student

vhdl verilog hdl hardware-description-language

Updated Oct 26, 2025
VHDL

jj1and / KRD

Verilog-HDL/VHDL project

python c hdl verilog-hdl xilinx-ip

Updated Feb 24, 2021
VHDL

alifa98 / CA-Fall2019

Computer Architecture Lab

vhdl circuit computer-architecture hdl logic-circuit

Updated Dec 23, 2019
VHDL

LuisMLopez-dev / Double-Dabble-Algorithm

This is a VHDL program for converting a binary number to a BCD (binary-coded decimal) number using the Double Dabble Algorithm.

programming fpga vhdl hdl xilinx-vivado nexys4ddr digital-circuit-design

Updated Jul 28, 2025
VHDL

sapertuz / xil_iic

vivado hdl hdl-ip-repo

Updated Nov 13, 2020
VHDL

icarogabryel / cnn-accelerator

CNN accelerator using radix-4 Booth's algorithm described in VHDL . It multiplies a 32-bit integer with a 7-bit constant from a 3x3 kernel and accumulates the results.

hardware accelerator cnn compressor ia hardware-designs computer-architecture hdl hardware-acceleration computer-organization integrated-circuits multiplier booths-algorithm

Updated Jul 4, 2025
VHDL

guilhermgonzaga / hdl-lab

VHDL assignments done at @ufms.

vhdl coursework hdl test-bench

Updated Dec 8, 2023
VHDL

dotrocks / dsd_project_2_security_system

AGU EEE DSD Capsule Project - Home Security System

security fpga vhdl hdl capsule agu

Updated May 20, 2025
VHDL

emeralddd123 / Parking-Assistant-FPGA

Parking Assistant Implemented with VHDL on Max10 DE Lite Board

fpga vhdl hdl parking-assistant

Updated Jun 2, 2025
VHDL

sampai97 / Modular-FFT-radix-2

VHDL modular Fast Fourier Transform based on Cooley-Tukey algorithm

vhdl fft cooley-tukey-fft hdl cooley tukey fourier-transform fastfouriertransform vhdl-code radix2 vhdl-project

Updated Aug 11, 2025
VHDL

Santana-DS / OAC_GRUPO-B3

OAC - Grupo B3 - Lucas Santana e Gabriel Castro (CIC0099 - UnB 2025/1)

cpu vhdl riscv hdl modelsim risc-v unb oac quartus pipeline-cpu harware multi-cycle-cpu uni-cycle-cpu

Updated Jul 14, 2025
VHDL

Jauler / shitty_cpu

I was just curious about how CPU's worked...

cpu hardware vhdl logic hdl hw

Updated May 19, 2021
VHDL

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Website: github.com/topics/verilog
Wikipedia: Wikipedia